Programmable Logic Devices: Simulation Lab 1

This 24-page simulation lab, made available by Maricopa County Community College District, provides students with experience working with programmable logic devices. The goal of the lab is to "learn the use of using Xilinx ISE 9.1i software by designing the circuits for a half adder its device and a 4-bits incrementer and its device." Learning objectives include:

• Create a half adder project in Xilinx ISE 9.1i using the free software ISE WebPACK.
• Use the Xilinx ISE 9.1i Schematic Editor to enter a graphical design in Xilinx ISE 9.1i.
• Compile and simulate the half adder design.  
• Create, compile, and simulate a half adder symbol in Xilinx ISE 9.1i
• Design the circuit for incrementer-4 using the half adder symbol
• Create, compile, and simulate an incrementer-4 symbol using Xilinx ISE 9.1i. 
• Use the Incrementer-4 to find Twos complement representations.

This lab is divided into the following sections: Acknowledgements, Lab Summary, Lab Goal, Learning Objectives, Grading Criteria, Lab Preparation, Equipment and Materials, and more. 

Prior to beginning this activity students should review the "How to use Xilinx ISE 9.1i" lab, which is available to view separately.